The present invention relates to a dynamic memory and, more particularly, to an apparatus for conducting error diagnosis and correction of a dynamic memory simultaneously with refresh operations.
Since, in a dynamic memory, stored data is lost with the lapse of time, it is necessary to repeat the read-out and write-back of the stored data at suitable intervals, and such an operation is called "refresh". In an MOS dynamic memory, for example, memory cells are essentially capacitors so that the data bits are stored in the form of charges in the capacitors and are gradually lost by a variety of leakage currents. A refresh operation can be effected by energizing row drive lines (also called "word selecting lines"). When a certain row drive line is energized, the contents of all the memory cells connected therewith are read out and amplified by their associated sense amplifiers until they are written back. A column address is used for selecting the sense amplifier output to be sent to an output circuit. In the dynamic memory of this type, therefore, a refresh operation can be achieved not only by the normal read and write operations requiring both row and column addresses but also by the memory drive operation for which only the row address is designated. A refresh of the latter type will be called a "RAS only refresh", which has usually been used in the prior art.
One of the problems accompanying a refresh is the accumulation of data errors. Data read out by the RAS only refresh is written back as it is without passing through an error detect/correct circuit which is disposed outside of the memory. As a result, errors having appeared once in the sense amplifier output for various reasons are left uncorrected and are accumulated through repetitions of refreshing until they cannot be corrected in a normal read operation.
A prior art apparatus for detecting and correcting the errors in association with the refreshing is disclosed in Japanese Patent Laid-Open No. 55-101199 which is entitled "Memory Refresh Apparatus". In the disclosed apparatus, a refresh is effected by designating a column address in addition to a row address in each refresh cycle to perform a read operation (A refresh of this type will be called a "read refresh"), with the read-out data being passed to an error detect/correct circuit. If a correctable error is detected, a special write cycle is started immediately (i.e. independently of the regular refresh cycle) so that the corrected data is written back. This prevents errors from accumulating. However, execution of the normal read or write operation has to be postponed until the end of that special write cycle inserted for error correction.
Besides, when the aforementioned read refresh is to be applied to a large memory, several problems arise. A large memory has a hierarchical structure. For example, a memory array is constructed of a plurality of memory packages, each of which contains a plurality of memory element groups. The memory address contains the memory element group address and the memory package address in addition to the row and column addresses. The row and column addresses are sent to a particular memory element group designated by the other addresses to designate a location therein. One read refresh operation can thus refresh only one row in a single memory element group. A remarkably large number of refresh cycles are required for refreshing throughout a large-scale memory by the read refreshing of that type. This results in increase in the number of the refresh cycles per unit time and decrease in the time period available for the normal read and write operations. If the aforementioned disadvantages are to be avoided by executing read refresh operations simultaneously in all the memory element groups, a large quantity of hardware is required to select one word to be checked from the output data coming from all the memory element groups.
There are other problems to be considered:rechecking after the corrected data has been written back; and measures according to the result of the recheck, such as the transfer of data to a spare memory area or securing the consistency of data during a series of processings starting from an error detection.